1. Field of the Invention
Embodiments of the invention relate generally to semiconductor devices and related methods of manufacture. More particularly, embodiments of the invention relate to semiconductor devices including a thin metal fuse and a thick metal bonding pad and methods for manufacturing the semiconductor devices.
2. Description of Related Art
Semiconductor devices are generally manufactured through several procedures performed in a sequence. These procedures may include, for example, fabrication (FAB) processes, electrical die sorting (EDS) processes, assembly processes, and test processes.
In a typical FAB process, a crystal ingot of semiconductor materials is sliced into a wafer, and various unit processes such as a diffusion process, a photolithography process, an etching process, and a deposition process for a thin layer are sequentially and repeatedly performed on the wafer to form electrical circuits.
After the FAB process, an EDS process is performed to inspect the wafer for processing defects such as defects affecting the electrical circuits. The EDS process typically comprises a pre-laser test, a laser repair process, a post-laser test and a back-grinding process. In the pre-laser test, each chip of the wafer is inspected for defects and electrical failure data is generated for any detected defects.
Next, in the laser repair process, repairable processing defects are corrected in accordance with the electrical failure data. Then, in the post-laser test process, some repaired dies on the wafer are selected and the selected dies are further inspected for defects. Finally, in the back-grinding process, a back or rear surface of the wafer is polished by a polishing unit such as a diamond wheel.
In the above-mentioned laser repair process, a fuse connected to a memory cell including detected defects, i.e., a “defective cell”, is cut by a laser, and the defective cell is replaced with a redundant cell within the same chip. By cutting the fuse, the laser repair process forces the defective cell to be electrically inactive and causes the redundant cell to be electrically active.
Conventionally, a bit line comprising polysilicon has been used as the fuse in a fuse box when the repairing process is performed by the laser repair process. However, due to the high integration density of contemporary semiconductor devices, several metal wirings are often stacked on or over the bit line. Accordingly, the metal wirings on the bit line are etched from the fuse box in the laser repair process to use the polysilicon bit line as the fuse.
Unfortunately, there may be many difficulties in forming the polysilicon fuse in the fuse box. In addition, the polysilicon fuse may be positioned so far below a top surface of the metal wirings that the laser repair process will require a high powered laser, and a nib end portion of the laser will be dispersed, potentially damaging a silicon wafer including the fuse.
For at least these reasons, when a semiconductor device has multilayer metal wirings, a barrier metal layer of a topmost metal wiring or a next topmost metal wiring has been used as the polysilicon fuse. However, where the barrier metal layer of the topmost metal wiring is used as the fuse, both the fuse and a bonding pad must be formed by a photolithography process using the same topmost metal wiring as an etching mask. As a result, the process for manufacturing the polysilicon fuse can be relatively complicated.
FIGS. 1A through 1C are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device including a fuse located in a next topmost metal wiring of a semiconductor wafer. More particularly, FIG. 1A illustrates a portion of the semiconductor device in which core and peripheral circuits are formed; FIG. 1B illustrates a fuse box of the semiconductor device; and FIG. 1C illustrates a bonding pad area of the semiconductor device.
Referring to FIGS. 1A through 1C, a memory cell (not shown) or at least one wiring structure is formed on a semiconductor substrate 10 such as a wafer. Silicon oxide is deposited onto substrate 10 to form an insulation layer 12.
A first barrier layer 14 comprising titanium (Ti) or titanium nitride (TiN), a first metal layer 16 comprising aluminum (Al) and a first capping layer 18 comprising titanium (Ti) or titanium nitride (TiN) are sequentially formed on insulation layer 12. Then, first capping layer 18, first metal layer 16 and first barrier layer 14 are sequentially patterned using a photolithography process to form a first metal wiring 20a. First metal wiring 20a includes a next topmost metal wiring and a metal fuse 20b. 
Silicon oxide is deposited onto first metal wiring 20a, metal fuse 20b, and insulation layer 12, so that a first inter-metal dielectric (IMD) layer 22 is formed on insulation layer 12 to a sufficient thickness to cover first metal wiring 20a and metal fuse 20b. First IMD 22 is then partially removed from insulation layer 12 by a photolithography process to form a via hole 24 through which first metal wiring 20a is partially exposed.
A second barrier layer 26 comprising titanium (Ti) or titanium nitride (TiN) is formed on a surface of first inter-metal dielectric layer 22 and on sidewalls and bottom of via hole 24. A second metal layer 28 is formed on second barrier layer 26 in such process that via hole 24 is filled with metal layer 28 and a top surface of metal layer 28 is planarized. A second capping layer 30 comprising titanium (Ti) or titanium nitride (TiN) is formed on metal layer 28. Then, second capping layer 30, metal layer 28 and second barrier layer 26 are sequentially patterned using a photolithography process to form a second metal wiring 32a. Second metal wiring 32a makes electrical contact with first metal wiring 20a through via hole 24 and includes a topmost metal wiring and a bonding pad 32b. 
Silicon oxide is deposited onto second metal wiring 32a, bonding pad 32b, and insulation layer 12, so that a second inter-metal dielectric layer 34 is formed on insulation layer 12 to a sufficient thickness to cover second metal wiring 32a and bonding pad 32b. Silicon nitride is deposited onto second inter-metal dielectric layer 34 to form a third inter-metal dielectric layer 36 on second inter-metal dielectric layer 34.
Third inter-metal dielectric layer 36, second inter-metal dielectric layer 34, and first inter-metal dielectric layer 22 are sequentially and partially removed from substrate 10 until top surfaces of metal fuse 20b and bonding pad 32b are exposed, thereby forming an opening 38 through which a fuse box and a bonding pad area are exposed.
Metal fuse 20b exposed through opening 38 is partially etched until first metal layer 16 of metal fuse 20b remains on first barrier layer 14 with a thickness of about 3000 Å. As a result, metal fuse 20b includes barrier layer 14 and first metal layer 16.
When first metal layer 16 of metal fuse 20b is partially etched, second capping layer 30 and metal layer 28 of bonding pad 32b, which are exposed through opening 38, are also partially etched so that bonding pad 32b includes second barrier layer 26 and metal layer 28. Accordingly, a thickness reduction of metal fuse 20b is performed by an etching process against first metal layer 16 of metal fuse 20b after opening 38 is formed.
Where a thickness of metal fuse 20b is excessively large, there is a problem that a first fuse connected to a defective cell may be difficult to cut using a laser during the laser repair process. Where the electrical power of the laser is increased to cut thick metal fuse 20b, there is a possibility that a second fuse connected to a non-defective cell adjacent to the defective cell may also be cut. However, the partial etching of metal fuse 20b against first metal layer 16 allows metal fuse 20b to have a small thickness such that an allowable error range of the laser repair process may be improved.
Unfortunately, because both the fuse box and the bonding pad area are simultaneously exposed through opening 38, metal layer 28 of bonding pad 32b is simultaneously etched with first metal layer 16 of metal fuse 20b by the same amount as first metal layer 16. As result, a thickness of bonding pad 32b also decreases in proportion to the reduction of metal fuse 20b, as indicated by the letter “A” in FIG. 1C.
A metal layer of the bonding pad requires a sufficient thickness to securely bond balls (e.g., solder balls) to the bonding pad in a packaging process for a semiconductor device to thereby ensure sufficient adherence between the balls and the bonding pad.
As a result, the excessive etching against metal layer 28 of bonding pad 32b reduces the thickness of bonding pad 32b. As a result, bonding pad 32b may have insufficient metal for a bonding agent between the balls and the bonding pad. Accordingly, the adherence force between the balls and the bonding force may be reduced and the balls may be undesirably separated from the bonding pad.